Flat panel displays have been in the market in the applications such as, TVs, monitors, cell phones, small phones, personal digital assistants (PDAs), etc. Particularly, due to its capability of being in large size and high definition, active matrix flat panel displays are widely integrated in large-sized TVs and high-definition hand-held devices.
An active matrix flat panel display generally includes an array of thin-film transistors (TFT) to control a light emission device. An exemplary TFT device 100 is shown in FIG. 1. Referring to FIG. 1, TFT device 100 includes a substrate 102, a gate electrode 104 disposed on substrate 102, a dielectric layer 106 disposed on substrate 102 and gate electrode 104, a semiconductor layer 108 disposed on dielectric layer 106, an etching stop 110 disposed on semiconductor layer 108, a drain electrode 112 disposed on one side of and in contact with semiconductor layer 108, a source electrode 114 disposed on another side of and in contact with semiconductor layer 108, a passivation layer 116 disposed on top of the above layers, a first contact hole 118 formed in passivation layer 116 to reach source electrode 114, a second contact hole 120 formed in passivation layer 116 to reach drain electrode 112, a pixel electrode 122 disposed in first contact hole 118, and a data electrode 124 disposed in second contact hole 120.
To form the TFT device as shown in FIG. 1, at least six masks are employed to form the pattern of the device layers. Specifically, one mask is needed for each of gate electrode 104, semiconductor layer 108, etch stop 110, source electrode 114 and drain electrode 112, contact holes 118, 120, and pixel electrode 122.
Etch stop 110 is employed to protect semiconductor layer 108 from being damaged by etchants during the patterning and etching steps to form source and drain electrodes 114, 112. This structure requires an extra photo mask to pattern etch stop 110 itself, which increases the fabrication cost and decreases the processing throughput. Further, passivation layer 116 is employed to protect the underlying device layers 104 through 114 from being affected by the environment.
Therefore, there is a need to reduce the number of the masks employed to fabricate a TFT device to increase manufacturing throughput and decrease the cost.